Copper pillar bumps were introduced in 2006 by Intel in their 65-nm “Yonah” microprocessor. As pin counts and interconnect densities increase, interest grew in copper pillar bumps as an alternative to conventional solder bumps for flip chip and wafer-level packaging.
Copper pillars offer advantages over solder bumps such as higher interconnect densities, higher reliability, improved electrical and thermal performance, and reduction or elimination of lead. While solder bumps collapse during solder reflow, copper pillars retain their shape in the x, y, and z directions. This allows for fabrication of finer bump pitches, smaller passivation openings, and fine redistribution wiring for higher interconnect densities.
However, during the manufacturing process the sidewalls of the copper pillar may be prone to chemical degradation during an etching process and at a subsequent assembly joining process oxidation may form on the copper pillar sidewalls resulting in poor pillar reliability and poor adhesion of copper to an underfill material.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved copper pillar bump in flip chip and wafer-level packaging that avoids the reliability concerns associated with conventional copper pillar bumps.